1. Field of the Invention
The invention relates in general to a finite impulse response (FIR) processor, and more particularly, based on Booth algorithm, to a programmable finite impulse response with a scalable dynamic data range.
2. Description of the Related Art
Filters of finite impulse response applied in a real-world applications have many advantages such as easy implementation, noise immunity, sharp cut-off frequencies, high stability and so on. The major operation of a FIR filter is the convolution realized by using adders, multipliers, and delay elements. However, a multiplier takes a lot of computation time to perform its function. In order to reduce the complexities, high-speed FIR filters without using multipliers have been proposed by many researchers. These multiplierless filters can be classified into a memory based approach, a canonical signed-digit (CSD) approach, and a Booth-algorithm approach.
The simplified FIR design in the above three approaches allows easy incorporation of programmability. However, scaleable dynamic ranges of input data and filter coefficients are not straightforwardly achievable. In the memory-based FIR design. the word length of input data and precision of filter coefficients are usually fixed for one memory configuration. In order to achieve scaleability, the memory cells have to be reconfigured and the connections between taps have to be rearranged. Due to a high cost of the original architecture for a large dynamic data range, the memory based FIR may not be a good candidate for scaleable design. In the CSD FIR design, filter coefficients are easily scaleable but functional units in each tap require the maximum word-length design. All CSD taps are directly addressed by every input datum using the fixed word-length hardware. When considering a large dynamic range of input data, the input data has to be partitioned into a sub-datum sequence. Hence, there is a need of the complicated tap design to support the FIR computing based on this sub-datum sequence. The scaleable CSD FIR cannot be realized at a low cost.
By employing Booth-algorithm, bit-level input data can be easily scaled for different dynamic ranges, and precision of filter coefficients can be scaleable due to the regular structure of each FIR filter tap.
A tap of a conventional FIR processor is shown as FIG. 1. The tap comprises a coefficient latch, a Booth decoder, an adder, a 2-to-1 multiplexor (MUX), and an accumulation latch. As shown in the figure, the FIR does not comprise a means for the application of Booth algorithm to scale a datum with dynamic ranges. Without configuring a connection between the input data and the filter coefficients, the function of the FIR is not flexible enough to process data with dynamic ranges.